You have been placing power ICs.
You have not been designing power supplies.
SMPS design is not about picking a controller IC and following its application note. It is about understanding what the inductor is doing, why the loop oscillates, where the switching loss goes — and making every component decision from that physical understanding.
Most engineers encounter power supply problems late — a rail that won't regulate, a switcher that fails EMC, a transformer running hot. This module reframes the problem before that happens. Read the five sections in order. Each one closes a gap you probably did not know you had.
Why Power Supply Design Matters
What a power supply actually does. Why linear regulators hit a wall. The design loop that every module in this bootcamp follows.
When Power Supplies Fail
Four real failure cases — thermal, oscillation, EMC, switching loss. The root cause in each was not a wrong component. It was an incomplete mental model.
Bench Validation & Correlation
A worked case where LTspice and the oscilloscope disagree. Separate probe artefact, missing parasitics, layout effects, and the real corrective action.
Tools & Simulation Stack
MATLAB as primary. LTspice as free alternate. TI WEBENCH for component validation. When to use each — and what none of them can replace.
The Design Mindset
Three physical principles that govern every switching topology. The cost curve of finding problems late. What this bootcamp actually trains.
A power supply has one job: take energy from a source and deliver it to a load at the right voltage, with the right regulation, at acceptable efficiency, without destroying itself or radiating interference. That sentence contains five independent design problems, each of which can fail independently.
Most engineers treat the power supply as an afterthought — a reference design from the controller IC's datasheet, copied and placed. That approach works until it doesn't. When it fails, there is no mental model to debug from. This bootcamp gives you that model.
The Design Loop
Every module in this bootcamp follows the same loop. Understanding it before Module 1 makes every subsequent module faster.
Input range, output voltage, current, isolation requirement
Before topology selection, the spec defines the constraints. Input range sets duty cycle limits. Output power determines which topologies are viable. Isolation requirement eliminates non-isolated options immediately.
Choose the topology, then size every component from equations
Inductor value from volt-second balance. Capacitor from charge balance. MOSFET from peak current and switching frequency. Every component value is derived, not guessed. This is the core of Modules 3 through 8.
Verify the design before a component is soldered
Simulation confirms the analysis. Layout determines whether the simulation result is achievable on a real board. Bench validation closes the loop — discrepancies between model and measurement are learning, not failure.
Linear vs Switching — the Numbers
🔋 Linear Regulator (LDO)
- Pass transistor operates in linear region — acts as a variable resistor
- Excess voltage dropped across pass element becomes heat: P = (Vin − Vout) × Iout
- Efficiency = Vout / Vin — regardless of load current
- At 12V in, 3.3V out: maximum efficiency is 27.5%. The remaining 72.5% is heat.
- Correct application: low dropout, low noise, low current, small Vin−Vout
⚡ Switching Regulator (SMPS)
- Switch operates fully on or fully off — no linear dissipation in steady state
- Energy stored in inductor or transformer, released to output — losses only at transitions
- Efficiency typically 85–95% regardless of conversion ratio
- At 12V in, 3.3V out: 92% efficiency — 8% loss vs 72.5% in the LDO case
- Correct application: any case where the linear thermal dissipation is unacceptable
The bench is a forgiving environment — short wires, clean supply, controlled load, no temperature variation. Your power supply is designed on the bench but runs in an enclosure at 70°C ambient, with a cable adding 50 mΩ to the output impedance and a load stepping from 10% to 100% in 10 µs. The failures below happened because the design did not account for that gap.
Expand each case. The symptom appears exactly as an engineer would encounter it in the field.
What Happened
The output capacitor was an aluminium electrolytic. Its ESR increases significantly with temperature — from 80 mΩ at 25°C to 220 mΩ at 55°C. Feedback compensation was designed around 80 mΩ. At 220 mΩ the ESR zero moved, phase margin collapsed below 15°, and the loop oscillated.
What Was Missed
ESR is a function of temperature. The datasheet value is measured at 100 kHz and 20°C — neither condition exists in the field. The simulation used nominal ESR. The bench test never ran the board warm. The failure was predictable and was not predicted.
What Changed
Output capacitor changed to ceramic (stable ESR across temperature). Compensation redesigned for worst-case ESR corners. Phase margin verified above 45° across the full temperature range in simulation before rework.
What Happened
The flyback transformer's leakage inductance was not measured — assumed negligible. At rated load, the RCD snubber clamped the drain spike adequately. At 2× load, peak current doubled, leakage energy quadrupled (E = ½LI²), and the snubber budget was exceeded. The spike exceeded BVDSS.
What Was Missed
Leakage inductance is rarely specified for custom wound transformers. It must be measured on the actual wound part. The design assumed a fixed spike amplitude — leakage energy scales with the square of current. This was never modelled and the snubber was never designed for current headroom.
What Changed
Leakage inductance measured on wound transformer. Snubber redesigned for 2× current headroom. FET BVDSS derated to 80% of clamped spike. Design validated at 150% load. Transformer rewound with interleaved primary/secondary to reduce leakage.
What Happened
Switching frequency was 400 kHz. The 3rd harmonic at 1.2 MHz exceeded CISPR 25 limits. The input filter was designed for attenuation at the fundamental — but its resonance at 800 kHz amplified the 3rd harmonic rather than attenuating it.
What Was Missed
An EMC filter is not a broadband attenuator. Its insertion loss is frequency-dependent and load-impedance-dependent. The filter was simulated with ideal source/load — not the actual LISN and converter input impedance. The resonance was never checked across the harmonic spectrum.
What Changed
Damping resistor added to suppress filter resonance. Switching frequency shifted to 500 kHz to move the 3rd harmonic away from the amplification region. Filter re-simulated with LISN model. Verified across operating load range.
What Happened
The gate driver was undersized. The FET gate charge of 12 nC required 3A peak gate drive current to achieve the 50 ns target switching transition. The selected driver was rated 1A. Actual rise time was 220 ns — switching losses were 4× the design assumption.
What Was Missed
Switching loss = ½ × Vin × Ipeak × (tr + tf) × fsw. Rise and fall time are set by gate driver current and gate charge — not by the FET alone. The simulation used ideal switches. The transition time was never calculated from actual gate charge and driver current capability.
What Changed
Gate driver upgraded to 3A. FET selected for lower gate charge at the same RDS(on). Switching transition recalculated and verified in LTspice with accurate gate resistance. Efficiency re-measured: 94.8% — within specification.
A simulation is useful only when it represents the as-built converter and the measurement represents the actual waveform. When the two disagree, the correct response is not to trust the cleaner result. First validate the measurement, then validate the model, then isolate the physical cause.
Synchronous buck, 500 kHz switching frequency, 60 V MOSFETs.
Approximately two ringing cycles near 95 MHz using nominal package and loop parasitics.
Long passive-probe ground lead used at the switch node. Ringing appears much worse than simulation.
Ground spring placed directly across the local switch-node reference. The first 9 V of “overshoot” was probe-loop artefact.
The Correlation Workflow
Start with a controlled first power-up
Inspect polarity and assembly, check resistance from input and output rails to ground, use a current-limited 24 V source, begin with no load, and monitor input current and output voltage before enabling a dynamic load.
Validate the measurement setup before judging the design
The long probe ground lead formed an additional inductive loop and exaggerated the high-frequency spike. Repeating the measurement with a ground spring reduced the observed peak from 51 V to 42 V. The measurement setup explained part of the discrepancy, but not all of it.
Compare the model with the as-built power loop
The simulation used 5 nH of commutation-loop inductance. The actual PCB loop, package leads, vias, and capacitor mounting contributed approximately 12–13 nH. The model also used simplified MOSFET output capacitance and omitted part of the diode-recovery current.
Update the model using measured evidence
After adding the as-built loop inductance, nonlinear Coss, capacitor ESL, and recovery current, LTspice predicts approximately 41 V peak with ringing near 70 MHz — closely matching the corrected 42 V, 72 MHz bench capture.
Apply a physical correction, then verify both model and hardware
A prototype RC snubber selected from the measured ringing response reduces the peak to about 32 V and damps the ringing within one cycle. The next PCB revision also shortens the hot loop and places the input ceramic capacitor directly across the switching pair.
| Stage | Peak Voltage | Ringing | Engineering Interpretation |
|---|---|---|---|
| Nominal simulation | 33 V | ~95 MHz | Model is optimistic because as-built loop and device parasitics are incomplete. |
| Initial scope capture | 51 V | ~60 MHz | Long probe ground lead adds a measurement loop and creates misleading overshoot. |
| Corrected probing | 42 V | ~72 MHz | This is the trustworthy hardware waveform used for correlation. |
| Updated simulation | 41 V | ~70 MHz | Model now represents the as-built loop, package, capacitor, and switching device behaviour. |
| After RC snubber | ~32 V | Damped within one cycle | Corrective action is verified in both simulation and measurement. |
Bench Validation Sequence Used Throughout the Bootcamp
| Validation Step | What to Observe | Common Mistake |
|---|---|---|
| Unpowered checks | Polarity, shorts, gate-to-source resistance, transformer continuity, rail resistance to ground | Applying full power before confirming assembly and static resistance |
| Current-limited startup | Input current, output rise, soft-start behaviour, abnormal heating | Starting at full voltage and rated current limit |
| Gate drive | VGS amplitude, rise/fall time, dead time, Miller plateau, negative spikes | Measuring gate voltage without referencing the source node correctly |
| Switch node or drain | Overshoot, ringing frequency, duty cycle, switching transitions | Using a long ground lead or an incorrectly rated probe |
| Output ripple | Switching ripple and low-frequency envelope under steady load | Large probe loop, no bandwidth limit, or measuring far from the output capacitor |
| Load transient | Undershoot, overshoot, recovery time, current limit response | Testing only at steady load and assuming regulation proves stability |
| Thermal validation | MOSFET, diode, inductor/transformer, capacitor and controller temperatures | Measuring only at room ambient or before thermal equilibrium |
| Loop response | Crossover frequency, phase margin, gain margin and operating-point variation | Using transient appearance alone as proof of loop stability |
Simulation is a verification tool, not a design tool. You cannot simulate your way to a correct design if you do not know what the correct result should look like before running it. Every simulation in this bootcamp runs after the hand calculation — it either confirms the analysis or reveals a discrepancy that needs explaining.
| Tool | Primary Use in This Course | Cost | Required? |
|---|---|---|---|
| MATLAB / Simulink | Primary simulation — switching waveforms, control loop Bode plots, transient response, closed-loop step response | Paid (student license available) | Yes — primary |
| LTspice | Alternate for every circuit — switching node, gate drive, snubber, parasitics. Shown side-by-side with MATLAB throughout. | Free | No — alternate |
| Scilab / Xcos | Open-source MATLAB alternative. Same models, different syntax. Shown where relevant for accessibility. | Free | No — alternate |
| TI WEBENCH | Component sanity check — cross-check derived values against a real controller IC. Not a design tool; a verification step. | Free (account required) | No — recommended |
| tools.vyomex.in | LLC resonant tank calculator — Module 8 extension for higher-power resonant converter design | Free | No — Module 8 only |
MATLAB — Control Loop Analysis
Transfer function modelling, Bode plots, phase margin measurement, step response. The right tool for stability analysis. Less suited for circuit-level switching transients.
LTspice — Circuit-Level Simulation
Transistor-level switching, parasitic effects, gate drive timing, snubber waveforms. Fast, free, accurate for transient analysis. Less suited for frequency-domain control analysis.
TI WEBENCH — Sanity Check
Enter your spec, get a controller IC recommendation with component values. Use it to cross-check your hand calculations. If WEBENCH agrees with you, you are probably right.
Hand Calculation — Always First
Before any simulation, derive the expected result. Duty cycle, inductor value, peak current, ripple — all calculable from equations you will know after Module 3. Simulation confirms; calculation predicts.
Every switching power supply topology — buck, boost, flyback, LLC — is a different implementation of the same three physical principles. An engineer who understands these principles can look at any unfamiliar topology and reason about its behaviour before opening a datasheet.
Volt-Second Balance
In steady state, the average voltage across an inductor must be zero. During on-time, inductor volt-seconds increase. During off-time, they must return to zero. This single equation determines the duty cycle of every non-isolated switching topology.
Applied in Modules 3, 4 — and implicitly in every subsequent module.
Charge Balance
In steady state, the average current into an output capacitor must be zero. Charge delivered during one part of the switching cycle equals charge removed during the other. This determines output voltage ripple and the capacitor RMS current rating.
Applied in Modules 3, 4, 6 — and in the Module 10 capstone.
Energy Conservation
Energy in = Energy out + Losses. Losses occur at switching transitions, in winding resistance, in core material, and in the control IC. The efficiency target is a design constraint calculated before layout — not a measurement outcome after the prototype.
Applied from Module 3 onward — thermal budget calculated before layout begins.
The Cost of Finding Problems Late
Power supply failures found late in the development cycle cost far more to fix than failures caught at the design stage. The timeline below is grounded in real hardware programme experience.
The course is structured in four pillars that build sequentially. Every module ends with either a design exercise or a simulation walkthrough — not just reading. Module 10 is the capstone: a complete 24V/2A flyback power supply from blank spec to layout-ready reference design document.
Ready to start Module 1?
Enroll in the full bootcamp — async HTML access with lifetime updates. Live cohort option available for guided design review.
These questions test what Module 0 covered — not what you already knew. If you cannot answer a question, the section number tells you exactly where to look.
Stop treating power as a black box.
Enroll in the SMPS Design Bootcamp. Ten modules, four topology pillars, MATLAB and LTspice simulations throughout — and a complete 24V/2A isolated flyback reference design as your capstone deliverable.