On a schematic, a wire is a perfect conductor: zero resistance, zero inductance, zero capacitance, infinite bandwidth. Connect pin A to pin B and the signal arrives instantly and perfectly at B. This is useful for capturing circuit topology — but it describes a circuit that exists nowhere in the physical world.

A PCB trace between two pins is a transmission line. It has: characteristic impedance Z₀ determined by its geometry and the surrounding dielectric, propagation delay proportional to its length, resistance that increases with frequency due to skin effect, dielectric loss that increases with frequency, and a return current path through the reference plane beneath it. None of these properties are on the schematic. All of them affect signal behaviour at the frequencies modern ICs operate at.

Every PCB contains a complete circuit that is not on any schematic. This invisible circuit consists of: parasitic inductance in every via barrel (approximately 0.5–1 nH per via), parasitic capacitance at every via pad (approximately 0.1–0.5 pF), mutual capacitance between adjacent traces (the crosstalk coupling capacitance), mutual inductance between traces that run parallel (the crosstalk inductive coupling), plane capacitance between power and ground planes, and package parasitic inductance and capacitance between the IC die and the board pins.

At low frequencies, this invisible circuit has negligible effect — the parasitic reactances are small. As frequency increases, the parasitic impedances grow. At some frequency — different for every design — the parasitic circuit starts to dominate the intended circuit. This crossover frequency is where SI/PI simulation becomes necessary.

Every signal current has a return current of equal magnitude flowing in the opposite direction. The schematic shows the signal path. It almost never shows the return path. On the PCB, the return current does not flow "through ground" in some abstract sense — it flows through the copper of the reference plane immediately beneath the signal trace, following the path of least inductance, which at high frequencies is the path directly underneath the trace.

When that return path is interrupted — by a split in the reference plane, by a plane cutout, by a via transition to a layer with no adjacent reference — the return current must detour around the obstruction. That detour creates a loop. A loop has inductance. Inductance at high frequencies means voltage drop — which means ground bounce, EMI radiation, and signal distortion. Every reference plane discontinuity in a high-speed design is a problem that is invisible on the schematic.

Lumped circuit theory — the theory that underlies schematic analysis — is valid when the wavelength of the signal is much larger than the physical dimensions of the circuit. The rule of thumb: lumped circuit theory is valid when the trace length is less than approximately λ/10 at the highest significant frequency of the signal.

The highest significant frequency of a digital signal is approximately the knee frequency: f_knee = 0.35 / t_rise. For a signal with a 1 ns rise time: f_knee ≈ 350 MHz. At 350 MHz in FR4, λ ≈ 150 mm / √4.2 × (1/0.35 GHz) × 300 mm/ns ≈ 207 mm. λ/10 ≈ 21 mm. Any trace longer than 21 mm carrying this signal is a transmission line — lumped circuit theory does not apply, and the trace must be treated as a distributed element.

A PCB trace above a reference plane is a waveguide — it guides an electromagnetic wave from driver to receiver. The signal does not flow through the copper like water through a pipe. The energy propagates in the electromagnetic field in the dielectric between the trace and the reference plane. The copper conductors define the boundaries of that field. This distinction matters: it explains why the return path (the reference plane) is as important as the signal trace, and why interrupting the reference plane interrupts the waveguide.

The characteristic impedance Z₀ is the ratio of voltage to current of a travelling wave on the transmission line — in the forward direction only, before any reflections. It is set entirely by the geometry: the trace width W, the height H above the reference plane, the copper thickness T, and the dielectric constant Dk of the material between them. It has nothing to do with the driver or receiver. It is a property of the physical structure.

For a microstrip (trace on the surface, reference plane below): Z₀ ≈ (87/√(Dk+1.41)) × ln(5.98H/(0.8W+T)). For H = 100 µm, W = 180 µm, T = 35 µm, Dk = 4.2: Z₀ ≈ 50 Ω. Change the trace width, the height to the reference plane, or the laminate — and Z₀ changes. This is impedance control. Getting it wrong means every signal on that trace sees a mismatch.

When a travelling wave encounters a change in impedance — a wider trace, a via, a connector, the end of the line — part of the wave is transmitted forward and part is reflected backward. The reflection coefficient: Γ = (Z_new − Z_old)/(Z_new + Z_old). If Z_new = Z_old, Γ = 0 — no reflection, the wave continues uninterrupted. If Z_new ≠ Z_old, a reflected wave is generated proportional to the impedance mismatch.

At a high-impedance receiver input (Z_input ≫ Z₀), Γ ≈ +1 — the wave is reflected with the same polarity, effectively doubling the voltage at the open end. At a short circuit (Z = 0), Γ = −1 — reflected with opposite polarity. At a matched termination (Z = Z₀), Γ = 0 — no reflection. This is why termination works: it makes the reflection coefficient zero at the problematic end of the line.

A signal on a PCB trace travels at approximately: v_p = c / √Dk_eff, where c = 300 mm/ns and Dk_eff is the effective dielectric constant (accounting for the fraction of field in air vs dielectric, typically 3.5–4.5 for common laminates). For Dk_eff = 4.2: v_p ≈ 300/√4.2 ≈ 146 mm/ns. A 100 mm trace introduces approximately 686 ps of propagation delay — regardless of the signal frequency.

This delay is why length matching matters in parallel buses: if one trace is 5 mm longer than another in a DDR data bus, the signal arrives 34 ps later — which must be within the setup time budget of the receiving device. At DDR5-4800 with a bit period of 208 ps, 34 ps is 16% of the bit period — significant.

At DC, the PDN is a resistive network. The VRM supplies voltage V_VRM. Current flows through the resistive path — copper planes, vias, package parasitics — to the IC power pins. Voltage drops along the way: V_drop = I × R_PDN. The IC sees V_VRM − V_drop. If this falls below VDD_min, the IC operates outside its specification. This is DC drop — the simplest PI failure mode and the easiest to simulate.

The resistances are small — milliohms — but the currents are large — amperes — and the budgets are tight: a 5V rail might tolerate 500 mV of drop, but a 1.0V FPGA core rail may tolerate only 50 mV (5% of VDD). 50 mV / 10A = 5 mΩ total PDN resistance budget. That is a tight budget and it is dominated by via resistance and copper spread resistance, not plane resistance.

When a digital IC switches state — even a single gate — it demands a brief burst of current from its power supply. The rate of that demand (dI/dt) depends on the rise time of the switching event. The faster the rise time, the higher the frequency content of the current demand. Inductance in the supply path opposes rapid current change: V = L × dI/dt. A high-inductance supply path means the current cannot respond fast enough — the voltage droops during the switching event.

This is why decoupling capacitors exist. The VRM is slow — its control loop bandwidth is typically 100 kHz to 1 MHz. Above that frequency, the VRM cannot respond. Bulk capacitors cover the next decade up to ~10 MHz. Small ceramic capacitors cover 10 MHz to ~500 MHz. Above ~500 MHz, on-die capacitance takes over. The PDN is a hierarchical charge reservoir system — each tier covering the frequencies the tier below cannot reach.

The unified way to think about PDN performance is impedance. At every frequency the IC demands current, the PDN must present low impedance — so that the voltage droop (V_droop = I × Z_PDN) stays within the IC's supply noise tolerance. The target impedance is a flat, low number from DC to the highest frequency the IC switches: Z_target = V_ripple_allowed / I_transient.

In practice, the Z(f) curve of a real PDN is not flat. It has: a low, controlled region where VRM and bulk caps dominate; a transition region with anti-resonance peaks where two capacitor tiers interact poorly; a rising region where board-level decoupling runs out; and a final flat region where on-die capacitance takes over. The engineer's job is to keep Z(f) below Z_target across the entire critical frequency range. Every peak above the target line is a frequency where the board will droop when the IC switches.

The worst-case PDN scenario is simultaneous switching: every output on a bus switching in the same direction at the same time. The total current demand is N × I_per_output. The voltage noise created is N × I × Z_PDN(f_switch). For a 32-bit bus with 20 mA per output and 50 mΩ PDN impedance at the switching frequency: V_SSN = 32 × 0.020 × 0.050 = 32 mV. On a 3.3V bus this is negligible. On a 1.2V DDR bus with ±30 mV noise tolerance, it is already over budget.

The fix is always the same: reduce Z_PDN at the switching frequency. The SSN is not a separate problem from AC PDN impedance — it is the time-domain consequence of the frequency-domain impedance. Fix the impedance and the SSN is fixed automatically.

A changing voltage on the aggressor trace creates a changing electric field in the space around it. Part of that field terminates on the victim trace, inducing a current proportional to the mutual capacitance Cm between the two traces and the rate of voltage change: I_induced = Cm × dV_aggressor/dt. This induced current splits at the victim trace — half flows toward the near end (where the driver is) and half toward the far end (where the receiver is), creating both NEXT and FEXT contributions.

Mutual capacitance Cm is determined entirely by geometry: trace spacing, trace width, height above the reference plane, and the dielectric constant of the surrounding material. Closer traces → larger Cm → more crosstalk. No amount of shielding or filtering at the schematic level changes this — only layout geometry does.

A changing current on the aggressor trace creates a changing magnetic field around it. Part of that field links with the victim trace through mutual inductance Lm, inducing a voltage: V_induced = Lm × dI_aggressor/dt. Inductive and capacitive NEXT add in the same direction on the victim trace. Inductive and capacitive FEXT subtract — in microstrip, capacitive FEXT dominates and FEXT is non-zero. In symmetric stripline, inductive and capacitive FEXT are equal and opposite — theoretical FEXT cancels.

Crosstalk amplitude scales approximately as 1/S² for loosely coupled traces, where S is the edge-to-edge spacing. Doubling the spacing reduces crosstalk by approximately 4× (−12 dB). This is the physical basis for the 3W rule: keep edge-to-edge spacing ≥ 3× the trace width. At S = 3W, the coupling is reduced to approximately 10% of tightly-coupled values — not zero, but small enough to be within noise margin for most interfaces.

The 3W rule is a rule of thumb, not a law. For interfaces with tight noise margins — DDR5 at 1.2V with ±30 mV tolerance — you may need 4W or 5W spacing on the most sensitive pairs. For LVCMOS 3.3V with ±300 mV tolerance, 3W is more than adequate. Apply the rule with the actual noise margin of your interface in mind.

NEXT (Near-End CrossTalk): Appears at the same end as the aggressor driver. Arrives simultaneously with the aggressor switching edge — it appears at the near end as soon as the aggressor starts switching. NEXT pulse width equals the rise time of the aggressor for short coupled lines; it saturates at a fixed amplitude for long parallel runs beyond the saturation length L_sat = t_rise × v_prop / 2.

FEXT (Far-End CrossTalk): Appears at the far end of the victim from the aggressor driver. Delayed by one propagation delay T_pd relative to the main signal. In microstrip: FEXT can be significant (capacitive and inductive contributions don't cancel). In stripline: FEXT is theoretically zero because the equal-and-opposite inductive and capacitive contributions cancel in a symmetric structure. In practice, small non-zero FEXT remains due to manufacturing asymmetry.

Adding a ground guard trace between aggressor and victim seems like an obvious fix. It works — but only if the guard trace is correctly connected to ground. "Correctly" means: via to ground at intervals no greater than λ/4 at the highest frequency of concern. At 2.5 GHz, λ/4 in FR4 ≈ 15 mm. Ground vias every 15 mm maximum.

A guard trace with ground vias only at the board edges — 150 mm apart — is a floating conductor at all frequencies above approximately 250 MHz. A floating conductor between an aggressor and victim does not shield — it intercepts energy from the aggressor and re-radiates it toward the victim. A floating guard trace typically makes crosstalk worse, not better. This is one of the most common layout mistakes made by engineers who understand the intent of guard traces but not the physics behind them.

At DC, current flows uniformly through the entire cross-section of a conductor. As frequency increases, electromagnetic skin effect pushes current toward the surface. The skin depth δ = √(ρ/πfµ₀) gives the characteristic depth where current density falls to 1/e of its surface value. For copper at 1 GHz: δ ≈ 2.1 µm. A 1 oz copper trace is 35 µm thick — at 1 GHz, essentially all current flows in the outermost 2.1 µm of the conductor.

This matters because the effective resistance of the conductor increases as the current is forced into a thinner and thinner surface layer. Conductor loss scales as √f — doubling the frequency increases conductor attenuation by approximately 1.41×. For a given trace geometry, conductor loss is fixed by the copper properties. The only layout variable is trace width — wider traces have more surface area for current to flow in, lower resistance per unit length.

The electric field of the signal wave propagates through the PCB laminate. As the field alternates at high frequencies, the polar molecules in the laminate reorient with each cycle, absorbing energy from the field and converting it to heat. The rate of this absorption is characterised by the loss tangent Df (also called tanδ): a dimensionless number that quantifies what fraction of the field energy is absorbed per cycle.

Dielectric attenuation scales linearly with frequency — doubling the frequency doubles the dielectric loss. For FR4 (Df ≈ 0.020): at 5 GHz, dielectric attenuation is approximately 3.7 dB/cm. For a 100 mm trace, that is 37 dB of loss at the Nyquist frequency of a 10 Gbps signal — catastrophic. This is why FR4 is inadequate for 10 Gbps and above, and why low-loss laminates (Megtron 6 with Df ≈ 0.004) exist: 5× lower loss tangent means 5× less dielectric attenuation at the same frequency.

When a channel has high insertion loss at the Nyquist frequency, the high-frequency content of each bit transition is attenuated more than the low-frequency content. This distorts the signal: the fast edge that the driver launched arrives at the receiver as a slower, blurrier edge. The energy from one bit "smears" into the adjacent bit period. This is inter-symbol interference (ISI) — and it is the primary cause of eye closure on long, lossy channels.

ISI appears in the eye diagram as reduced eye height and eye width. It is data-pattern-dependent: a long run of consecutive identical bits (high CID) stresses the channel more than alternating 10101010... patterns. This is why PRBS31 (31-bit maximum CID run) reveals ISI that PRBS7 (7-bit maximum run) hides — the specification requires the longer pattern because real data has long runs.

A transient solver advances through time in small steps, computing the state of the circuit (voltages and currents) at each time point. It uses: IBIS models for IC drivers and receivers (V-I curves and waveform tables), RLGC or W-element models for traces (distributed parameters per unit length), and S-parameter models for connectors and complex structures. The output is a time-domain voltage waveform at each observation point.

What it assumes: The circuit model is correct. The IBIS model accurately represents the real IC. The stackup data in the RLGC model matches the fabricated board. The termination topology in the model matches the actual circuit. Every wrong assumption produces a wrong result — and the solver cannot detect these errors. It solves whatever model you give it.

A frequency domain solver computes the circuit's response at each frequency point — impedance, insertion loss, return loss — without simulating time-domain behaviour. For PDN impedance: it injects current at the observation port and measures voltage at each frequency, computing Z(f). For S-parameter extraction: it solves Maxwell's equations in the board geometry at each frequency, computing how electromagnetic fields propagate through the structure.

Where it can be wrong: The board geometry model must match the actual board. The dielectric properties (Dk, Df) must match the actual laminate at the operating frequency — not just at 1 MHz. The port placement must reflect the actual observation point on the physical board. The solver is accurate; the geometry and material data are where errors enter.

A 3D electromagnetic solver (HFSS, CST, Momentum) solves Maxwell's equations in full 3D — computing the exact electromagnetic field distribution around a structure. This is used for: extracting S-parameters from via structures that are too complex for analytical models, characterising connector launches at frequencies above 5 GHz, and modelling antenna radiation from board structures. The 3D solver is more accurate than circuit models for complex 3D structures — but also far more computationally expensive. Use it for components where simpler models are known to be inadequate.

Every simulation has a hierarchy of inputs, and an error at any level propagates through all levels below it. From most critical to least critical:

Level 1 — Material properties: Dk and Df at the operating frequency for your specific laminate. Wrong Dk changes every impedance calculation in the entire simulation. Wrong Df changes every insertion loss prediction. If you don't have the frequency-dependent Dk(f) and Df(f) curves from your laminate supplier, everything above a few hundred MHz is approximate.

Level 2 — Stackup geometry: Layer thicknesses, copper weights, layer order. A wrong prepreg thickness changes impedance calculations proportionally. Most boards import with the EDA tool's nominal stackup, which may differ from the fabricated board by ±10%.

Level 3 — Component models: IBIS models for drivers and receivers, S-parameters for passives. A generic IBIS model introduces error for every simulation on every net connected to that device.

Level 4 — Simulation setup: Corner conditions, PRBS pattern, bit rate, observation port placement. Wrong setup parameters produce results that are accurate for a different operating condition than the one you intended to test.

What it looks like: The board passes all testing at room temperature. At 85°C or under thermal load, it produces intermittent data errors on one or more interfaces. The errors are not reproducible at low temperature.

Physical cause: Either (a) timing violation at the Slow Weak SI corner — the IC driver at high temperature and low VDD has a slower edge rate, the signal arrives later at the receiver, and the timing margin that exists at room temperature is consumed by the slower edge. Or (b) PDN IR drop worsens at high temperature because copper resistance increases ~0.4%/°C — 60°C rise adds ~24% more resistance, pushing a marginal DC drop over the limit. These two failure modes produce similar symptoms but different fixes — simulation at the correct corner resolves the ambiguity before board re-spin.

What it looks like: BER is acceptable during low-traffic operation. Under heavy write traffic — specifically, large write bursts — BER climbs. Reducing traffic makes the BER disappear. Reducing the write burst length makes it intermittent rather than persistent.

Physical cause: PDN AC impedance above Z_target at the write burst switching frequency. Write bursts demand maximum simultaneous current from the PDN. If Z_PDN(f_switch) exceeds Z_target, VDD droops during the burst. The IC operates at reduced VDD during the period when it is most critical. SI simulation with ideal VDD completely misses this — the PDN must be validated before the SI simulation means anything.

What it looks like: A control signal that is not switching produces spurious transitions. The spurious transitions correlate with switching activity on an adjacent high-speed bus. The problem disappears when the adjacent bus is placed in a low-activity or idle state.

Physical cause: Crosstalk. The switching bus (aggressor) couples energy onto the quiet net (victim) through mutual capacitance and inductance. If the induced noise exceeds the victim receiver's input threshold, the receiver captures a spurious transition. The correlation with aggressor activity is the diagnostic fingerprint — no other failure mode produces this pattern. Fix: layout change only — increase spacing, reduce parallel run length, or re-route the aggressor to a different layer with a reference plane between it and the victim.

What it looks like: A SerDes interface operates at multiple line rates. At one specific rate, BER is unacceptable. At all other rates — faster and slower — BER is fine. Changing the rate by 5% makes the failure disappear.

Physical cause: Via stub resonance. A through-hole via in the signal path has a stub resonance at a frequency close to the Nyquist of the failing data rate. The resonance creates a deep insertion loss notch — 10–20 dB — at that frequency, making it impossible for the channel to pass that specific data rate. The data-rate-specific nature of this failure is unique to via stub resonance; no other SI failure mode has this frequency-specific sensitivity. Fix: back-drill the via stub to remove the resonance. Calculate f_stub = c/(4×L_stub×√Dk) — it will match the failing Nyquist within measurement error.

What it looks like: Board passes all functional testing on the bench. After 500–2000 hours of field operation, devices begin to fail. Failure rate accelerates with temperature. The failed devices show ESD protection diode degradation under failure analysis.

Physical cause: Latent overshoot damage. Under Fast Strong conditions (fast process corner + low temperature + high VDD), the SI simulation would show overshoot above the absolute maximum input voltage rating. Each switching event drives a small current through the ESD clamp diode. The diode does not fail immediately — but it degrades slightly with each event. Over millions of switching events in field operation, the diode degrades below its specified performance and the input fails. A bench test runs for hours — not long enough to accumulate the damage threshold. SI simulation at the Fast Strong corner, compared against the absolute maximum rating, would have predicted this before first silicon.

A digital waveform contains harmonics set primarily by transition time. A slow repetition rate does not guarantee a low-frequency interconnect problem. A 10 MHz clock with a 200 ps edge excites the interconnect into the GHz region; the trace must respond to the edge, not to the label printed on the clock tree.

A trace becomes distributed when the wave has enough time to travel a meaningful fraction of the interconnect while the source is still transitioning. The exact threshold is an engineering choice, but the comparison must always be between flight time and edge time.

At high frequency, return current concentrates near the signal conductor on the nearest reference plane because that path minimises loop inductance. If the signal changes reference planes without a nearby stitching path, the return current detours, the loop area grows, and both radiation and local ground/reference noise increase.

Positive Γ means the reflected voltage has the same polarity as the incident wave; negative Γ means opposite polarity. Open ≈ +1, short ≈ −1. Real drivers and loads are frequency dependent, so use this as the first mental model.

Target impedance is a design bound derived from allowed rail ripple and load-current change. It is not a universal number.

Frequency-dependent loss reshapes edges and creates memory. Different bit histories arrive at different levels/times: inter-symbol interference.

Use transition time and electrical length.

Real return paths have resistance and inductance. Fast current creates local reference motion.

It is proof only for the model, boundary conditions, corner, and observation point you actually simulated.

Real capacitors have ESR/ESL and can interact to create anti-resonance. Placement and mounting inductance matter.