SI/PI starts with one question:
where does current flow, and what impedance does it encounter?
On a real PCB, signals and power do not move through ideal wires. Time-varying current propagates through distributed geometry, return paths, packages, vias, planes and dielectric materials. Those structures create resistance, inductance, capacitance, coupling and delay. SI/PI engineering is the process of predicting when those physical effects become large enough to consume voltage, timing or noise margin — and deciding what evidence is needed before changing the design.
You are not learning a sequence of buttons in one simulator. The same physical reasoning applies whether the analysis is performed in HyperLynx, SIwave, Sigrity, ADS, a field solver, SPICE, or a measurement environment.
For every worked case, write the result you expect before revealing the explanation. If the observed evidence does not match the prediction, the correct engineering response is to revisit the hypothesis or model — not to force the conclusion.
A schematic answers what is connected. SI/PI asks how that connection behaves in space and time. Many prototype failures appear only after geometry, package, return path, material and switching conditions are included.
A schematic wire has no delay, impedance discontinuity, mutual coupling or distributed loss. A real PCB interconnect has all of them. At sufficiently slow transitions the ideal-wire approximation is excellent; as electrical length grows, the approximation loses information that the receiver actually sees.
Vias, pads, antipads, planes, packages and connectors contribute distributed R, L and C. Their values are not universal constants: they depend on geometry and the return path. Treat handbook numbers only as rough screening estimates; use extracted or measured models when the structure is electrically significant.
At high frequency, return current tends to follow the route that minimises loop inductance, normally close to the signal on its reference conductor. Plane splits, layer changes without a nearby return transition, voids and connector discontinuities can force a larger loop and increase reference movement, coupling and radiation.
Distributed behaviour depends on the relationship between interconnect flight time and signal transition time. A useful screening method is to estimate the edge knee frequency and wavelength, but λ/10 is a heuristic — not a physical cliff. Near the boundary, the correct decision depends on allowable reflection, topology and noise/timing margin.
A useful transmission-line model should let you predict the sign, timing and approximate cause of a waveform disturbance before a solver shows it.
The signal is an electromagnetic wave guided by the trace and its return conductor. The field occupies the dielectric around the conductors; copper loss, dielectric loss, reference discontinuities and nearby conductors all modify that guided wave.
Z₀ is a property of the cross-section and materials, not the receiver resistance. Width, copper thickness, height to reference, dielectric properties and solder mask can all shift it. A closed-form equation is useful for intuition; fabrication field-solver values are preferred for final geometry.
Example screening equation for microstrip: Z₀ ≈ (87/√(εr+1.41))·ln(5.98H/(0.8W+T)). With H=100 µm, W=150 µm, T=35 µm and εr=4.2, the estimate is ≈50 Ω. Treat the equation as an approximation, not a fabrication guarantee.
At a boundary, Γ=(Z₂−Z₁)/(Z₂+Z₁). Γ>0 gives a same-polarity reflected voltage; Γ<0 gives opposite polarity; Γ=0 gives no reflection at that boundary. Open and short are useful limiting cases, while real CMOS inputs and packages are frequency dependent.
At the receiver, the first reflection occurs when the incident wave reaches the load. At the source, the reflected wave returns after the round-trip delay. Multiple impedance changes produce multiple echoes. This is why transient waveform timing and TDR location can be combined to isolate a discontinuity.
Power integrity is not “does the regulator output the right voltage?” It is whether the voltage at the device pins stays inside its allowed window for the actual current waveform and current-return geometry.
At steady load, ΔV≈I·R. The resistance includes planes, neck-downs, vias, connectors, package paths and return current. Allocate source tolerance, board drop and load tolerance explicitly; do not assume the entire datasheet voltage range belongs to the PCB.
Fast load change is limited by inductance: V=L·dI/dt. The effective source of current changes with frequency among regulator/output network, bulk storage, board capacitors, plane/package paths and on-die capacitance. The crossover frequencies are design-specific — not fixed decade boundaries.
Z_target≈ΔV_allowed/ΔI is useful for designing and reviewing a PDN. Keep the load-point impedance below the target over the frequency range where the relevant current spectrum has energy. A peak above target is a risk only if the load event excites that frequency strongly enough.
When many I/Os switch, their current waveforms add through shared package, via and plane inductance/resistance. The resulting rail/ground movement depends on edge rate, simultaneous activity, package topology and return path. The general relation is frequency-domain ΔV(f)=Z_PDN(f)·ΔI(f), plus local shared-inductance effects. A single “N×I×Z at f_switch” number is only a rough toy model.
| Region | Likely dominant path |
|---|---|
| Low | Regulator control and bulk network |
| Mid | Board capacitors + mounting/plane inductance |
| High | Package and on-die network increasingly dominate |
Crosstalk is a distributed field-coupling problem. The most useful design variables are spacing, coupled length, reference-plane distance, layer relationship, edge rate and termination. There is no universal “3W solves it” rule.
A changing aggressor voltage drives current through mutual capacitance: i≈C_m·dV/dt. More field intercepted by the victim means more coupling. Bringing the reference plane closer can confine more field to the aggressor-reference pair and reduce victim coupling.
A changing aggressor current couples through mutual inductance: v≈M·dI/dt. Geometry, return paths and coupled length set the mutual coupling. Faster edges generally increase both capacitive and inductive excitation.
Near-end crosstalk is present in both microstrip and stripline. Far-end crosstalk depends on the difference between even- and odd-mode propagation. In an ideal homogeneous symmetric stripline, first-order FEXT can cancel; real asymmetry, loss and discontinuities make non-zero FEXT possible. In microstrip, differing modal velocities generally make FEXT more visible.
Crosstalk falls as spacing increases and rises as parallel coupled length grows, but the exact relationship depends on trace width, height to reference, stackup and termination. Rules such as 3W are screening heuristics. For a critical victim, extract or simulate the actual geometry and compare induced voltage/timing against the receiver margin.
A guard conductor that is poorly tied to reference can itself become a coupled resonant structure. Stitching pitch should be electrically small over the relevant bandwidth and selected from the geometry/field problem — not from a universal λ/4 rule. Often, simply increasing spacing or using a closer solid reference is cleaner than inserting a guard trace.
Loss is frequency dependent, so it does more than reduce amplitude. When higher-frequency components are attenuated or delayed differently from lower-frequency components, the received edge changes shape and one symbol can influence the next.
For copper, skin depth δ≈√(ρ/(πfµ)). Once skin depth is small compared with conductor thickness, AC resistance rises roughly with √f. Surface roughness and current crowding can further increase high-frequency loss. Exact attenuation depends strongly on trace geometry and roughness model, so avoid generic dB/cm numbers.
For a low-loss TEM-like line in a homogeneous dielectric, a useful estimate is α_d≈πf√ε_r·tanδ/c Np/m. Microstrip uses an effective dielectric participation, and real laminate Dk/Df vary with frequency and test method. Use vendor frequency-dependent data for sign-off.
At 5 GHz with εr=4.2 and Df=0.020: α_d≈2.14 Np/m≈18.6 dB/m≈0.186 dB/cm. Over 100 mm, dielectric loss alone is therefore ≈1.86 dB — not 18.6 or 37 dB. Total channel loss must still include conductor/roughness, vias, connectors, packages and other discontinuities.
If the channel attenuates high-frequency content more strongly, transitions become slower and the received level depends on previous symbols. That is inter-symbol interference. Long-run and pseudo-random patterns can reveal different channel memory than a simple 1010 pattern; the correct stress pattern is interface-specific.
The decision framework is tool-independent. A solver answers the mathematical problem you give it; it does not know whether your stackup, package, load, corner or observation point matches the hardware.
Combines active I/O models with distributed interconnect/network models to calculate voltage/current versus time. Useful evidence includes overshoot, settling, threshold crossings, propagation delay, pattern dependence and eye construction.
Computes quantities such as Z(f), S11/S21, resonances and coupling across frequency. It is the natural view for PDN impedance and broadband channel/discontinuity characterisation.
Useful for via fields, connector launches, packages, cavities and other complex transitions. Higher fidelity is only useful if port definitions, material data, meshing and boundary conditions are correct.
Materials: Dk/Df, copper conductivity/roughness and frequency dependence.
Geometry: as-built widths, heights, vias, reference planes, connector/fixture.
Device models: correct pin, I/O standard, package, PVT/IBIS corner, receiver load.
Experiment: stimulus, activity, termination, observation point, thresholds, bandwidth and environmental condition.
This bootcamp does not teach button sequences. It teaches the analysis category, model boundary and evidence required for the engineering question.
| Engineering question | Analysis / evidence type | What the result can support |
|---|---|---|
| Will a topology ring or violate threshold? | Pre-layout distributed transient analysis | Reflection timing, overshoot/undershoot, termination sensitivity and topology trade-off. |
| What does the routed board do? | Post-layout extracted interconnect + transient/frequency analysis | Effect of actual lengths, layers, coupling, vias and transitions. |
| Where is steady-state rail voltage lost? | DC drop / current-density analysis | IR drop, current crowding and resistive bottlenecks. |
| At which frequencies is the PDN vulnerable? | Frequency-domain impedance analysis | Z(f), resonance/anti-resonance and target-impedance margin. |
| How does a connector/via/channel transmit and reflect energy? | S-parameter / EM extraction | S11/S21/coupling and broadband discontinuity behaviour at defined ports. |
| What sampling margin does a model predict? | Transient/statistical eye or timing analysis | Model-based voltage/time margin under stated stimulus, corner and jitter assumptions. |
| What did the physical board produce? | Oscilloscope / VNA / TDR / rail measurement as appropriate | Measured waveform, network response, impedance or timing at a defined physical reference plane. |
| Is the model credible for this decision? | Simulation-to-measurement correlation | Agreement of features and sensitivity under matched conditions; residual mismatch and uncertainty documented. |
Functional errors appear only at the highest data rate. Lowering the rate removes the failure.
Wrong stackup, omitted connector loss, probe loading, stimulus mismatch, fabrication variation or an incomplete driver / receiver model.
Identify which mismatch is large enough to explain the measured eye closure before modifying the board.
Freeze the comparison conditions
Write down the conditions for both results. The team aligns the observation point, data rate, bit pattern, output drive, slew setting, termination, supply voltage, temperature, scope bandwidth, filtering and reference threshold. The measured TIE histogram is generated in the oscilloscope analysis software from acquired edge timing.
Check the measurement path before blaming the board
- Repeat the capture with the specified low-capacitance active probe.
- Apply the characterised fixture / cable de-embedding file.
- Confirm that bandwidth limiting and clock-recovery settings match the intended compliance or engineering method.
- Move the probe only after recording the exact physical observation point.
The eye improves slightly, but the failure remains. Probe loading is a contributor, not the root cause.
Audit the model against the as-built board
- The simulation used the release stackup; the fabricator's as-built report shows a larger dielectric height on the signal layer.
- The connector was represented as an ideal through-connection; its launch and via field were not included as an S-parameter block.
- The receiver observation point in simulation was at the PCB pad, while measurement included the connector, fixture and probe path.
Use independent evidence to isolate the root cause
TDR shows a local impedance discontinuity at the connector launch. The as-built stackup recalculation shows that the routed trace is below the intended impedance. A VNA or validated connector model shows additional insertion loss and return loss that the original simulation never included.
Correct the model, then correct the design
- Replace nominal geometry with the as-built stackup and actual routed dimensions.
- Insert the connector / launch S-parameter model at the correct reference planes.
- Include package and receiver loading at the intended observation point.
- Use the same stimulus and corner conditions as the bench test.
- For the next board spin, retune the trace geometry and improve the connector launch / return-via structure.
Verify correlation instead of declaring victory from one screenshot
The updated simulation now reproduces the measured eye shape and the location of the dominant degradation. After the layout correction, both simulation and measurement show improved eye height and width, and the intermittent mask hits disappear under the matched test conditions.
Before comparing any simulated and measured waveform, confirm all of the following:
Real hardware symptoms are rarely unique to one mechanism. Use the pattern to rank hypotheses, then choose a controlled experiment that makes those hypotheses predict different outcomes.
Possible mechanisms: slower driver/receiver timing, higher copper resistance, regulator/PDN drift, material changes or component tolerance. Discriminator: separate timing margin, steady DC rail drop and dynamic rail disturbance under the same temperature.
Possible mechanisms: direct crosstalk, SSN/shared return, PDN droop, clock/reference modulation or thermal loading. Discriminator: aggressor on/off plus simultaneous rail/ground/timing observation.
Strong hypothesis: crosstalk — but not proof. Shared reference movement can produce the same correlation. Change spacing/coupled length in the model or switch the aggressor while monitoring local ground/rail to separate mechanisms.
Possible mechanisms: via/connector resonance, channel notch, clock spur, equalization-mode boundary or protocol configuration. Discriminator: frequency response and a geometry/parameter sweep. A resonant mechanism should move when electrical length changes.
Repeated overstress is one possible mechanism, but do not infer it from elapsed time alone. If failure analysis shows clamp degradation, correlate measured/simulated overshoot and clamp current with absolute-maximum/transient ratings and environmental stress. Reliability conclusions require device-specific qualification evidence.
This foundation module supplies the physical intuition that every later SI/PI decision depends on. Do not treat equations as isolated formulas. For each topic, connect physical mechanism → observable signature → analysis method → design lever. That chain is the core skill used throughout this learning path.
Repetition rate tells you how often an edge occurs. Rise/fall time tells you how quickly the voltage/current changes during each edge. The faster the transition, the wider the useful spectrum and the more strongly discontinuities and coupling are excited.
If a wave can travel a significant distance while the source transition is still occurring, voltage and current are no longer uniform along the route. The interconnect must be treated as distributed. Compare t_flight with t_r, and use λ/10 only as a screening heuristic.
A layer transition is not complete until the return current can transition too. Signal vias without nearby reference vias can enlarge the loop. Crossing a plane split can be worse because the return current has no local continuous path at all.
A 3.3 V GPIO toggles at 20 MHz, but the buffer rise time is 400 ps. The route is 80 mm long and ε_eff ≈ 4. Would you screen this as lumped or distributed?
Separating SI and PI is useful for analysis, but the hardware does not know those labels. Signal current closes through the PDN, switching outputs inject current into power and ground structures, and supply motion changes transmitter/receiver behaviour.
| Mechanism | Physical cause | What you may observe | Best first evidence |
|---|---|---|---|
| Reflection | Impedance discontinuity | Overshoot, undershoot, ringing, multiple edges | Transient + TDR |
| Crosstalk | Electric/magnetic field coupling | Victim noise correlated with aggressor activity | Aggressor on/off simulation or measurement |
| SSN / ground bounce | Shared return inductance × simultaneous di/dt | Quiet outputs move when many outputs switch | PDN/SSN transient correlation |
| PSIJ-like behaviour | Supply variation changes edge timing | Edge position correlated with rail ripple | Time-correlated rail + signal measurement |
| Loss / ISI | Frequency-dependent conductor/dielectric loss | Slow settling, pattern dependence, eye closure | Insertion loss + impulse/eye |
A receiver occasionally mis-samples only when a nearby 16-bit bus switches. The victim trace is unchanged. Name three different mechanisms that could create the correlation.
Positive Γ means the reflected voltage has the same polarity as the incident wave; negative Γ means opposite polarity. Open ≈ +1, short ≈ −1. Real drivers and loads are frequency dependent, so use this as the first mental model.
Target impedance is a design bound derived from allowed rail ripple and load-current change. It is not a universal number.
Frequency-dependent loss reshapes edges and creates memory. Different bit histories arrive at different levels/times: inter-symbol interference.
Use transition time and electrical length.
Real return paths have resistance and inductance. Fast current creates local reference motion.
It is proof only for the model, boundary conditions, corner, and observation point you actually simulated.
Real capacitors have ESR/ESL and can interact to create anti-resonance. Placement and mounting inductance matter.
These calculators are screening tools, not sign-off solvers. Their purpose is to train engineering intuition: if you change rise time, impedance, current step or symptom, you should know which result moves and why.