Why Simulation

Stop guessing. Start knowing.

Most PCB engineers design by feel — rules of thumb, past experience, and hope. Simulation replaces all three with actual data.

Without simulation

→Route at 50 Ω "because that's the rule" — and hope it works
→Discover eye diagram failures at first prototype bring-up — after fab
→Guess at decoupling capacitor placement with no data to back it up
→Find voltage hotspots only when boards fail in the field
→Debug crosstalk by trial and error — layer changes, re-spins
→Write findings reports based on experience, not measured results

With HyperLynx simulation

→Verify impedance, termination, and eye margin before fabrication
→Catch SI failures in simulation — not at first prototype bring-up
→Optimise decoupling placement with PDN impedance data
→Identify IR drop hotspots on DC voltage maps before the board is fabricated
→Quantify crosstalk between coupled nets and verify guard traces
→Produce professional findings reports with actual simulation screenshots

Curriculum

9 Sessions — what happens in each one

Every session begins with a focused concept, moves to hands-on simulation in HyperLynx, and ends with a group exercise. No passive lectures.

Phase 1 — Foundation

S1

Foundation

SI/PI fundamentals & the layout mindset

What signal integrity and power integrity mean. From trace to transmission line — the core mental model shift. Common SI failures: reflections, crosstalk, ringing. Common PI failures: IR drop, PDN resonance, SSN. HyperLynx product family overview.

HyperLynx tasks: Interface orientation · Load demo board · Explore stackup editor · Browse netlist

S2

Foundation

Transmission lines, impedance & eye diagrams

Characteristic impedance — the formula and what controls it. Reflections, termination strategies (series, parallel, AC). Rise time and bandwidth. Eye diagrams — how they're constructed. Eye height = voltage margin, eye width = timing margin. JEDEC compliance masks.

HyperLynx tasks: Build LineSim schematic · Change impedance · Remove termination · Add series terminator · Open eye diagram · Overlay JEDEC mask

Phase 2 — SI Simulation

S3

SI Simulation

HyperLynx setup & EVAL board import

BoardSim vs LineSim. The .hyp file format. Importing the EVAL board. Stackup verification — Dk, Df, copper thickness, layer assignments. Net explorer. Component viewer. Handling missing models.

HyperLynx tasks: Import EVAL board · Verify stackup · Find target nets · Identify driver and receiver ICs

S4

SI Simulation

First SI simulation — IBIS models & transient analysis

IBIS model format — what it contains. Assigning driver and receiver models. Simulation parameters — rise time, PRBS, supply voltage. Probe placement. Reading oscilloscope output — overshoot, undershoot, ringing, settling time.

HyperLynx tasks: Load IBIS files · Assign models · Configure simulation · Run transient · Place probes at TX, midpoint, RX · Measure overshoot and settling time

S5

SI Simulation

Crosstalk analysis on the EVAL board

Aggressor and victim nets. NEXT — near-end crosstalk. FEXT — far-end crosstalk. Parallel run length vs spacing. Ground guard traces. Crosstalk in differential pairs. Batch crosstalk mode across all coupled nets.

HyperLynx tasks: Enable coupled simulation · Select aggressor net · Run NEXT and FEXT · Reduce trace spacing · Add guard trace · Run batch report

Phase 3 — PI Simulation

S6

PI Simulation

PI fundamentals & DC drop simulation

PDN from the IC's perspective. Target impedance — how to derive it. Copper plane resistance. Via resistance. Decoupling capacitors — placement rules. DC drop analysis — hotspots, colour-coded voltage maps. Green is good, red is a problem.

HyperLynx PI tasks: Import EVAL board · Identify power nets · Define current loads · Set VRM location · Run DC drop · Identify lowest-voltage point · Calculate total IR drop

S7

PI Simulation

AC PDN impedance & SSN analysis

PDN impedance vs frequency. Target impedance line. Capacitor self-resonant frequency. Anti-resonance. Bulk capacitors vs decaps vs on-die capacitance. SSN — simultaneous switching noise. Decap placement optimisation.

HyperLynx PI tasks: Run AC impedance sweep 1 kHz–1 GHz · Plot Z vs frequency · Overlay target impedance · Move decap · Change capacitor value · Run SSN simulation

Phase 4 — Capstone

S8

Integration

Results interpretation & design fixes

Reading SI results — eye height, width, overshoot, jitter. Reading PI results — IR drop, impedance peaks, SSN. Root cause framework. SI fixes: trace width, spacing, termination, via stub removal. PI fixes: decap repositioning, plane widening, via count. Simulation report structure.

HyperLynx tasks: Load all SI + PI results · Use report generator · Annotate failures · Implement one fix · Compare before/after waveforms · Export PDF report

S9

Capstone

Independent full-board SI + PI analysis

Run a complete SI and PI analysis on the EVAL board from scratch — independently, with no guidance. Define your own simulation scope. Run all simulations. Interpret all results. Produce a professional findings report. Deliver a 3-minute verbal summary to the group.

Deliverable: Top 3 SI risks + top 2 PI risks found · Full HyperLynx screenshots · Professional findings report exported as PDF

What You Gain

8 things you can do independently after 9 sessions

All simulations are on a real EVAL board. IBIS models for all components are provided. No prior simulation experience assumed.

🔬

Run SI simulations independently

Set up and run transient signal integrity simulations in HyperLynx BoardSim and LineSim on any PCB layout — without step-by-step guidance.

👁️

Read and interpret eye diagrams

Construct, read, and interpret eye diagrams. Connect each result — eye height, width, overshoot, jitter — back to a specific layout cause.

〰

Analyse crosstalk on real nets

Run NEXT and FEXT crosstalk analysis on coupled nets. Identify the worst net pairs and verify the effect of spacing and guard trace changes.

⚡

Run PI simulations independently

Set up and run DC drop and AC PDN impedance simulations in HyperLynx PI. Identify voltage hotspots, resonance peaks, and SSN risks.

🎯

Optimise PDN decoupling in simulation

Use the PDN impedance curve as a diagnostic tool. Adjust decoupling capacitor placement and values in simulation before changing the layout.

🔍

Trace failures to their root cause

Systematically trace any SI or PI simulation failure back to its specific root cause in layout geometry, stackup, component selection, or routing.

🛠️

Propose and verify design fixes

Translate simulation findings into specific, actionable layout changes. Run the fix in simulation to confirm it resolves the issue before any physical change.

📄

Produce a professional simulation report

Write a clear, structured findings report with risks, root causes, and design recommendations — suitable for design reviews and client deliverables.

Who Is This For

Basic PCB or electronics background is enough

No prior simulation experience needed. HyperLynx must be installed and licensed from Session 3 onwards.

🔧

PCB Layout Engineers

You design boards daily but haven't used simulation to verify your layout decisions. This gives you the tool and the skills to do it independently.

⚙️

Hardware Design Engineers

You spec the design but rely on layout engineers to get it right. Simulation lets you verify SI/PI constraints before the board goes to fab.

🎓

Engineers Targeting Roles in EDA

HyperLynx experience is a differentiator on a hardware engineering CV. This training gives you real simulation experience on a real board.

What You Need

Prerequisites by phase

You don't need everything on day one. Requirements build gradually through the programme.

Before Session 1

Just show up

Nothing required except basic PCB or electronics background. No simulation experience assumed.

Before Session 2

HyperLynx installed

HyperLynx must be installed on your laptop. LineSim must launch without errors. Eval license or full license both work.

Before Session 3

HyperLynx fully licensed

EVAL board .hyp file and IBIS model package are provided by the instructor before Session 3 via WhatsApp group.

FAQ

Common questions

Do I need prior simulation experience?›

No. The first two sessions build your foundation from scratch. You need basic PCB or electronics background — understanding what a trace is and what a signal does. No HyperLynx or simulation experience is assumed.

What version of HyperLynx do I need?›

Any version of HyperLynx that includes BoardSim, LineSim, and the PI Module. Both eval licenses and full commercial licenses work. If you have access through your company, that's fine. Contact us before enrolling if you're unsure about your license.

Will sessions be recorded?›

Yes. Session recordings are shared with the batch group via WhatsApp for review. They are not publicly released — they are for enrolled students only.

What if I miss a session?›

You can catch up using the session recording. Since the batch is small (10 students), the pace is adjustable. Reach out via WhatsApp and we'll make sure you don't fall behind.

Is this an online or in-person training?›

Online only. Sessions are conducted via video call. This is an India-only batch scheduled at 7 PM IST to suit working engineers and students. You simulate on your own machine — the instructor demonstrates and guides in real time.

What is provided by the instructor?›

The EVAL board .hyp layout file and the IBIS model package for all EVAL board components are provided by the instructor before Session 3. You do not need to source these yourself.

Can I get a refund if I can't attend?›

Full refund if you withdraw before Session 1 starts. No refund after the batch begins — seats are limited and we cannot fill them at short notice. If you have a genuine emergency, contact us and we'll find a solution.

How many seats are actually left?›

6 seats as of the date this page was published. Seats are confirmed only after payment — a WhatsApp message or email does not hold your seat. If the batch fills before you pay, you'll be on a waitlist for the next batch.

Your Instructor

Trained by someone who uses these tools at work

AG

Abhishek Garg

Founder, VyomEx · FPGA IP Core Designer · SI/PI Simulation Trainer

I use HyperLynx for SI/PI simulation in professional hardware development. I run the Advanced PCB Design Bootcamp and the Hardware Design Fundamentals course on VyomEx EDU. This SI/PI training programme is built from the exact workflow I use on real production board designs — not from a textbook. The EVAL board, the IBIS models, and the simulation exercises are all things I have used or derived from real design work. The batch is small by design — 10 students means every session is interactive, every question gets answered, and every engineer leaves with real simulation results in hand.

FPGA IP Core Design SI/PI Simulation HyperLynx PCB Signal Integrity EMI/EMC Design Hardware Bring-Up

Interested in the next batch?

Saturday & Sunday · 7 PM IST · 9 sessions · Online · India batch.
Reach out directly to register your interest for the next cohort.

WhatsApp [email protected]

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