Cohort 01 starts 30 May. Early Bird closes May 17 or when first 5 seats fill. Reserve your seat →
Intensive Masterclass · Cohort 01 · Limited Seats
PCB Design for

EMI / EMC
Compliance

Engineering the boards that pass — before they enter the lab.

A 20-hour live intensive for working hardware engineers — designed to build the engineering reasoning behind boards that pass EMI compliance the first time, not after three re-spins.

Format
4
Live Days
Duration
20
Total Hours
For Engineers
2–10
Years Experience
Cohort
Limited
Seats · Cohort 01
Physics-first, not rule-first
No tool tutorials — pure engineering reasoning
30+ years combined experience
Lifetime session recordings included
"This is not a course. It is how senior engineers design PCBs that pass EMI — before they enter the lab."
The VyomEx EDU Philosophy
Four things that change
how you design forever.
Not certificates. Not completion badges. Engineering judgement you'll use on every board after this.
01

Design PCBs that pass EMI

Build the engineering judgement to clear pre-compliance the first time — without expensive lab-driven re-spins eating your schedule and budget.

02

Reason, don't memorise rules

Learn the physics under every layout decision so you can defend choices, adapt them to any product class, and stop second-guessing yourself in reviews.

03

Run senior-level reviews

Identify EMI risk from a placement file alone. Do pre-compliance reviews the way 15-year veterans do — before a single trace is routed.

04

Build a reusable framework

Walk away with stackup templates, routing rulebooks, and review checklists you'll use on every future board — not just for this one.

Eight modules. Twenty hours.
One mental model.
Each module starts from physics and ends with a decision framework you can apply on the next board on your desk. No tool tutorials, no vendor talk — only engineering reasoning.
MOD 01
EMI Engineering Mindset
2 hr
Think like an EMI engineer, not a layout engineer.
Why EMI failures actually happen in industry. Source-Path-Antenna mapping to PCB topology. Switching noise and spectral behaviour. Return current as a design parameter. Reading EMI problems from waveform behaviour. Real-world cost of EMI mistakes.
→ Mental model: EMI as physics, not compliance checklist
MOD 02
Stackup Engineering & Field Control
3 hr
Choose stackup like a senior engineer.
2L vs 4L vs 6L vs 8L — quantified EMI comparison. Plane-pairing strategy for EMI and impedance. Field containment through stackup. Dielectric impact and trade-offs. Practical: design multiple stackups for different product classes.
→ Deliverable: stackup decision framework for your product class
MOD 03
Return Current & Plane Physics
3 hr
Master the #1 EMI concept in PCB design.
Return current vs frequency — deep analysis. The minimum-impedance path concept. Plane splits: the EMI mechanism, not just the rule. Stitching-via placement science. Return-path inductance and CM noise generation.
→ Never place a via without understanding why again
MOD 04
Component Placement & Hot Loop Control
2 hr
Eliminate EMI issues before routing begins.
Functional zoning for multi-domain boards. Hot-loop identification across DC-DC, drivers, IO. Loop inductance estimation. Decoupling placement optimisation. Clock and crystal placement under EMI sensitivity.
→ EMI risk spotted at placement — not at re-spin
MOD 05
Routing for EMI Control
3 hr
Route with signal integrity AND EMI awareness.
Loop-area minimisation in practice. High-speed routing rules. Differential pair behaviour and CM conversion. Via impact on EMI. Reference-aware routing strategy. Length mismatch and DM-to-CM conversion through asymmetry.
→ Every routing decision has a reason, not just a rule
MOD 06
Power Integrity + EMI
2 hr
Control EMI at the source level.
Decoupling network design — beyond placement. Capacitor ESR/ESL impact on EMI. Ferrite-bead selection criteria. Power-loop control. PDN impedance vs EMI resonance. Practical: design a PDN that meets EMI compliance.
→ Deliverable: PDN design worksheet
MOD 07
Filtering & Interface EMI Control
2 hr
Design working filters — no more trial & error.
CM vs DM noise from an engineering-first view. Power-entry filter design. Signal-line filtering for USB, CAN, Ethernet. Filter placement rules and why they matter. Why filters fail because of layout. CM choke selection with real parameters.
→ Filter design from physics, not from application notes
MOD 08
EMI Debugging & Pre-Compliance Thinking
3 hr
Think like a review engineer before tape-out.
Identify EMI risk from a PCB review alone. Pre-compliance mindset and methodology. Common failure patterns and their signatures. Quick fixes vs root-cause fixes. Case studies: hot-loop radiation, cable-as-antenna, 2-layer failure. Live Q&A and case study review.
→ Leave with a pre-tape-out review process you'll use on every board
Four days. Five hours a day.
Built for working engineers.
Sessions run in focused blocks so you can attend without clearing your entire week.
Day 01 · Sat 30 May
EMI Foundations + Stackup
Module 1 — EMI Mindset (2 hr)
Module 2 — Stackup Engineering (3 hr)
5 hours
6:00 PM – 11:00 PM IST
Day 02 · Sun 31 May
Return Currents + Placement
Module 3 — Return Current (3 hr)
Module 4 — Hot Loop Control (2 hr)
5 hours
6:00 PM – 11:00 PM IST
Day 03 · Sat 6 June
Routing + Power Integrity
Module 5 — Routing for EMI (3 hr)
Module 6 — Power Integrity (2 hr)
5 hours
6:00 PM – 11:00 PM IST
Day 04 · Sun 7 June
Filtering + Debugging + Live Q&A
Module 7 — Filtering (2 hr)
Module 8 — Debugging + Q&A (3 hr)
5 hours
6:00 PM – 11:00 PM IST
👨‍💻
Principal Industry Mentor
Vijay Baraiya
Hardware Architecture & Global Compliance · 21 Years

Two decades of hands-on hardware engineering across design, development, and product deployment. Vijay brings the industry perspective — the failure modes, the compliance wars, and the decisions that never make it into textbooks.

"Good hardware engineering is not about which tool you use. It's about why you make the decisions you make."
EMI / EMC Hardware Architecture Signal Integrity Power Integrity PCB Design
Lead Instructor & Curriculum Architect
Abhishek Garg
FPGA IP Core Designer & SI/PI Simulation Trainer · 9 Years

Founder of VyomEx EDU. Practicing SI/PI simulation trainer with deep roots in FPGA design and high-speed PCB engineering. Abhishek brings the physics-first teaching approach — built from the depth he always wanted when learning himself.

"We don't teach. We share the depth we always wanted — so you don't get stuck where we already got trapped."
SI / PI Simulation FPGA IP Design PCB Engineering HyperLynx High-Speed Design
30+
Combined Years
Hardware architecture, global compliance, SI/PI simulation, and FPGA design — two engineers, one mental model, built to transfer what took us decades to learn.
Four tools you'll use
on every board after this.
Not course notes. Not slides. Engineering references built for the bench, written with the reasoning preserved — not stripped out.
📋
EMI PCB Design Checklist + Stackup Templates
A pre-tape-out checklist plus ready-to-use stackup configurations for consumer, industrial, and RF product classes. Built from the modules, not from a generic template.
Pre-tape-out reference
📐
Placement & Routing Rulebook
Engineering-driven rules with the reasoning preserved — not just the rules stripped from context. Understand why each rule exists so you can adapt it when the next board is different.
Reasoning-first reference
🔧
Filter Design Cheat Sheet
CM/DM filter selection and design reference, written for the bench, not the textbook. Real parameters, real component selection criteria, real failure modes to avoid.
Bench reference
🎞️
Lifetime Recordings + Bootcamp Access
All sessions recorded for unlimited replay. Plus full self-paced EMI/EMC Interactive Design Bootcamp included — 16 modules, 365-day access, separately valued at ₹14,999.
Included — ₹14,999 value
Three windows. One cohort.
Pricing is structured by enrolment window — not by value. The masterclass content, mentorship, and deliverables are identical across every tier.
Your Details — required before payment
May 18 – May 30
Standard
25,000
Standard enrolment for confirmed cohort. Same content, same deliverables.
  • All 8 modules · 20 hours live
  • EMI Checklist + Stackup Templates
  • Placement & Routing Rulebook
  • Filter Design Cheat Sheet
  • Lifetime session recordings
  • Self-paced bootcamp included (₹14,999)
May 31 – June 5 · Subject to availability
Final Call
30,000
Late enrolment window. Subject to seat availability only.
  • All 8 modules · 20 hours live
  • EMI Checklist + Stackup Templates
  • Placement & Routing Rulebook
  • Filter Design Cheat Sheet
  • Lifetime session recordings
  • Self-paced bootcamp included (₹14,999)
Comparable India Training
₹35K–75K
Typical market rate
This Masterclass
From ₹19,999
Early bird pricing
Bootcamp Bonus
Included
₹14,999 value · free
"We don't teach you everything — nobody can. We share the depth we always wanted when we were learning ourselves. So you don't get stuck where we already got trapped."
VyomEx EDU · Shared by Engineers