You don't need to understand why the layout works.
Until the board fails.
Software can hide hardware for a while. But the first time a board oscillates unexpectedly, an IC gets hot, or the signal is noisy for "no reason" — you need the foundation. This module builds it before you need it.
A vocabulary reference
Every technical term used across Modules 1–12, defined precisely with context. Stop Googling mid-session.
A concept ladder
The ten ideas that everything else builds on — in the correct order, with no assumed knowledge.
An electricity & components primer
Ohm's Law, current paths, return paths, and how every passive component behaves in a real layout.
A schematic reading guide
How a layout engineer reads a schematic — not symbol by symbol, but as functional blocks with signal flow.
A complete design-review preview
Follow one mixed-signal controller from requirements and stackup through placement, routing, EMI, thermal, DFM and release review.
This bootcamp assumes you have an interest in electronics. It does not assume you know PCB layout. If you've ever wondered:
— "Why do I need to put the capacitor right next to the IC pin?"
— "What does a ground plane actually do?"
— "Why does trace width matter if copper is copper?"
— this module answers those questions first, so every layout decision in Modules 1–12 makes immediate sense.
Once you hold this model, ground planes make sense. Decoupling capacitor placement makes sense. Return path routing makes sense. The entire bootcamp is elaborating on this one idea from different angles — getting closer and closer to why real boards fail.
Entry point
Electricity, components, schematic reading, current loops and basic PCB construction. This removes assumed knowledge so beginners can enter the course without memorising rules they do not understand.
Advanced outcome
Stackup decisions, placement priority, power and return paths, mixed-signal partitioning, EMI containment, thermal design, manufacturing review and release evidence on complete boards.
The Big Picture
What a PCB is, what it contains, and how copper becomes a working circuit
A PCB (Printed Circuit Board) is a structured sandwich of materials that mechanically supports components and electrically connects them through patterned copper. It is not a wire mesh — it is an engineered system where every material choice, every layer, and every copper trace has a consequence.
The structural core. Glass-reinforced epoxy. Electrically insulating, mechanically rigid, thermally stable. Standard thickness: 1.6mm. Determines the board's dielectric properties.
Your traces, pads, and planes. Etched from copper foil laminated to FR4. Typically 35µm (1oz) or 70µm (2oz). Width and thickness determine how much current a trace can carry.
Solder mask (green/black/red coating) protects copper and prevents solder bridges. Silkscreen prints component labels. Neither conducts electricity.
Multilayer boards (4, 6, 8 layers) add internal copper layers laminated between FR4 prepreg sheets. Internal layers are usually dedicated power and ground planes — enabling cleaner signal routing on outer layers.
| Type | Copper Layers | When to use | Main limitation |
|---|---|---|---|
| Single-layer | 1 (top only) | Very simple circuits, cost-sensitive, basic LED boards | Cannot cross traces — forces component placement constraints |
| Double-layer | 2 (top + bottom) | Most hobby and medium-complexity designs. Default starting point. | No dedicated plane layers — ground plane on bottom limits signal layers |
| 4-layer | 4 (top + GND + PWR + bottom) | Any design with high-speed signals, switching power, or EMI sensitivity | Higher cost, more complex DFM rules |
| 6+ layers | 6, 8, 10… | Dense BGA routing, RF boards, complex mixed-signal designs | Cost, lead time, increased via complexity |
The Concept Ladder
Ten ideas in the right order — each one makes the next possible
These ten ideas are the prerequisite for everything else in the bootcamp. They appear in order — each concept uses the previous one. If one doesn't click, everything after it will feel like memorization instead of engineering.
Course Map
What each day covers and how they connect — click any day to expand
The modules form a deliberate sequence: engineering thinking → layout fundamentals → advanced techniques → manufacturing readiness. Each module builds on all previous ones. Every technical term you'll encounter is defined in the glossary of this module.
Keyword Glossary
Every technical term used across Modules 1–12 — defined before you need them
Electricity Basics
Voltage, current, resistance, and the return path — the four ideas every layout decision uses
Electrical pressure. The force pushing electrons through a conductor. Always measured relative to a reference — on your PCB, that reference is ground. "3.3V rail" means 3.3V above the GND net.
The actual flow of electrons, measured in Amperes. This is what heats your traces. When you size a trace width for a power net, you are sizing it for current — not for voltage.
Opposition to current flow. Your copper traces have resistance — thinner and longer means more resistance. More resistance means more voltage drop and more heat generated in the trace itself.
Same idea as the Ohm's Law box above, worked in reverse: given a current, what trace width keeps heating under control? This uses the actual IPC-2221 external/internal-layer formula — the same one professional trace-width calculators use.
IPC-2221: A = (I / (k·ΔT^0.44))^(1/0.725), k=0.048 external / 0.024 internal. Always add margin over the bare minimum and check your fab's DFM limits.
Current always flows in a complete loop. Always. Kirchhoff's Current Law: what flows out of a source must return to it. For every milliamp going forward through a signal trace, there is exactly the same current returning through the ground network.
Most beginners obsess over the forward path (the signal trace) and treat ground as passive. Ground is not passive — it carries identical current. The shape and quality of the return path determines noise, EMI, and stability equally to the forward trace.
A ground plane provides a low-impedance return path for all signals simultaneously. Return current flows directly beneath each signal trace through the plane — minimizing the current loop area and therefore EMI radiation.
DC (Direct Current) flows in one direction steadily. Your power supply, your battery — these are DC. Most ICs consume DC power from their VCC pins.
AC (Alternating Current) reverses direction periodically. Mains power is AC at 50/60Hz.
Core Components
What each component does — and its specific PCB layout implication
You will encounter these on every board. Understanding their physical behavior — not just their schematic symbol — is what makes a layout decision engineering rather than guesswork.
| Component | What it does | PCB layout implication |
|---|---|---|
| Resistor | Limits current. Voltage dividers. Pull-up / pull-down on logic lines. | Usually non-critical placement. Exception: high-frequency termination resistors must be within 1–2mm of the driver output. |
| Capacitor | Stores charge. Filters noise. Decouples power supply transients from IC pins. | Decoupling caps must be as close as possible to IC VCC pins. Every mm of trace adds inductance that reduces effectiveness at high frequency. |
| Inductor | Stores energy in a magnetic field. Filters. Core of switching regulators. | Inductors in buck/boost circuits radiate magnetic fields. Keep away from sensitive analog or RF traces. Short, wide traces for current path. |
| Diode | One-way current valve. Polarity protection. Rectification. | Schottky diodes in power paths need wide copper for current. Fast-switching diodes radiate — short traces. Always check polarity in footprint. |
| MOSFET / BJT | Switching and amplification. Controls large currents with small signals. | High-current MOSFETs need thermal management. Gate drive trace should be short — long traces add inductance that causes ringing and slow switching. |
| Voltage Regulator | Converts one DC voltage to another, stably. Linear (LDO) or switching. | Input and output caps must be placed per datasheet — often within 2–5mm. Feedback resistors extremely sensitive to noise coupling from nearby traces. |
| Crystal / Oscillator | Provides a precise clock frequency reference to an MCU or processor. | Most sensitive component in most designs. Traces must be short. Keep away from RF, high-current, and switching traces. Surround with guard ring connected to GND. |
Every digital IC draws current in rapid bursts — millions of times per second as its internal logic switches. When it suddenly demands a burst of current, the power supply cannot respond instantly. The supply voltage at the IC's VCC pin dips.
A decoupling capacitor placed close to the IC acts as a local charge reservoir. It pre-charges from the supply, then instantly delivers charge when the IC demands it — preventing the voltage dip.
Your IC switches internally at 100MHz. You've got a 100nF cap. Pick how far it sits from the VCC pin and see whether it can actually keep up.
Leads pass through drilled holes and are soldered on the opposite side. Mechanically strong. Used for connectors, large caps, inductors, and anything needing mechanical strength. Occupies space on both sides of the board. Harder to assemble automatically.
Soldered directly onto pads on one surface. Smaller. Suitable for reflow oven assembly. Enables higher density. Standard for all modern ICs, resistors, caps. Most of your board will be SMD.
SOIC — Small Outline IC. Gull-wing leads. Common for op-amps, drivers.
QFN — Quad Flat No-lead. Bottom pads only. Excellent thermal. Common for power ICs.
DIP — Dual In-line Package. Through-hole. Classic through-hole IC shape.
0402 / 0603 / 0805 — Resistor/cap sizes in inches (04×02 mil footprint).
BGA — Ball Grid Array. Pads under the chip. Requires multilayer + X-ray inspection.
Reading Schematics
How a layout engineer reads a schematic — not symbol by symbol, but as a system
Module 2 of the bootcamp asks you to read schematics and identify critical signal paths. Without a systematic approach, you'll miss the layout-critical information buried in the schematic.
Identify power entry points
Where does power enter? What voltages? Regulated externally or internally? Trace the power section first — it determines where to place your power ICs, bulk caps, and power trace widths.
Identify the main ICs and their function
MCU, power management IC, sensor, radio — each has a different layout sensitivity. The MCU's crystal is highly sensitive. A power IC's switching node radiates. An RF module needs a keepout zone.
Trace signal paths and classify them
Which signals are high-frequency? Which are sensitive analog inputs? Which carry high current? Annotate the schematic before opening your PCB tool. High-frequency signals need short traces with reference planes.
Find datasheet layout recommendations
Every IC datasheet has a "PCB layout" or "application" section. These specify critical component placement distances, keep-out zones, and ground connection requirements. They are engineering specifications — not suggestions.
Understand net names and what they carry
Net names like CLK_48M, MOSI, SDA tell you the signal type and sensitivity. GND is your return path — understand every connection to it. VCC/VDD are power — understand which ICs share a rail and why isolation might be needed.
What does each pin do? Which are analog inputs? Which are high-speed digital? Which carry high current? This table determines your placement strategy.
Decoupling cap values. Power supply noise limits (PSRR spec). Thermal ratings. Maximum junction temperature. These constrain your layout directly.
The reference circuit the manufacturer tested. Use this as your schematic starting point — every component value and connection has a reason.
Often a section literally titled "PCB Layout Considerations." Contains: critical component placement, keep-out zones, thermal pad connections, ground pour requirements. These are your highest-priority layout constraints.
Exact mechanical dimensions for creating or verifying footprints. Pad sizes, pitch, land pattern recommendations. Incorrect footprints cause assembly defects or no-contact opens.
Seven real symptoms. Pick the root cause for each — this is exactly how Days 2–12 will test you, except with a real board in front of you instead of four options.
If this was the prerequisite,
now comes the bootcamp.
Module 0 gave you the language and the mental model. The full bootcamp takes that foundation and applies it across 12 modules of real PCB design — placement, routing, stackup, return paths, EMI, debugging, and tape-out readiness — with 84 scenario-based quizzes and live calculators built into every module.
Complete Board Review
One representative board reviewed from requirements to release evidence
The project is a 4-layer controller with 24 V input, a 5 V buck converter, a 3.3 V LDO, an STM32-class MCU, an 8 MHz crystal, USB, isolated RS-485 and a low-level analogue sensor input. It is complex enough to expose the interactions that isolated layout rules hide.
Requirements and block diagram
Capture input range, load current, interfaces, isolation, environment, board outline, connector positions and compliance targets before selecting a stackup.
Schematic annotation
Classify high-current loops, clocks, reset, analogue inputs, differential pairs, protection components, thermal parts and layout-constrained components.
Stackup and fabrication capability
Choose a 4-layer stackup with uninterrupted ground beneath signal layers. Confirm minimum trace, spacing, drill, annular ring, copper weight and controlled-impedance capability with the fabricator.
Placement priority
Lock connectors and mechanical features, then place power loops, crystal, decoupling, analogue input chain and interface protection before non-critical passives.
Power routing and decoupling
Minimise the buck commutation loop, size high-current copper, connect decouplers with short pin-to-cap-to-ground paths and verify regulator feedback is sensed from a quiet point.
Clocks and sensitive signals
Keep the crystal loop compact, prevent fast digital routes from entering the analogue region, route USB as a referenced differential pair and keep reset away from noisy edges.
Return-path review
Trace the return beneath every fast signal. Add stitching vias at layer transitions and connector boundaries. Do not allow high-speed routes to cross splits, voids or plane cut-outs.
EMI, ESD and interface containment
Place TVS and filters at the connector entry, provide a short discharge path, control common-mode current and keep external-cable currents away from the logic ground path.
Thermal review
Estimate dissipation, check copper-spreading area, thermal vias, airflow assumptions, nearby temperature-sensitive components and enclosure conditions.
DFM and assembly review
Verify footprints, courtyard clearance, solder-mask slivers, paste apertures, component orientation, test access, panelisation assumptions and hand-solder constraints.
Gerber or ODB++ verification
Inspect the actual manufacturing output rather than trusting the PCB editor view. Check layer polarity, apertures, drills, slots, solder-mask openings, plane clearances and fabrication notes.
Final design-review report
Record assumptions, unresolved risks, simulations, calculations, rule waivers, review comments and sign-off status. A board is released with evidence, not because it “looks complete”.
Bad Board Review Cases
Six layout defects that can pass DRC and still fail electrically or in manufacturing
CASE 01Decoupling capacitor is close in millimetres but far electrically
The capacitor shares a long narrow neck and a distant ground via with other loads.
Decoupling capacitor is close in millimetres but far electrically
The capacitor shares a long narrow neck and a distant ground via with other loads.
Likely symptom
Supply-pin droop, reset sensitivity or high-frequency noise despite the correct capacitor value.
Evidence
The pin-to-cap-to-ground current loop is long. The capacitor is visually nearby but trace and via inductance sit in series with it.
Correction
Route pin → capacitor pad → dedicated ground via with the smallest practical loop. Use multiple vias when current and frequency require them.
CASE 02Crystal network is placed too far from the MCU
Long oscillator traces run beside a GPIO bus and over a plane discontinuity.
Crystal network is placed too far from the MCU
Long oscillator traces run beside a GPIO bus and over a plane discontinuity.
Likely symptom
Intermittent startup, excess clock radiation or frequency instability sensitive to touch and temperature.
Evidence
The oscillator loop area is large and the return path is discontinuous. Fast adjacent signals inject noise into a high-impedance network.
Correction
Place crystal and load capacitors beside the oscillator pins, keep the loop compact, avoid unrelated routing through the area and follow the MCU vendor's grounding guidance.
CASE 03Switching node copper extends beneath the analogue section
The buck SW node is enlarged for “current capacity” and routed under the sensor amplifier.
Switching node copper extends beneath the analogue section
The buck SW node is enlarged for “current capacity” and routed under the sensor amplifier.
Likely symptom
Switching-frequency spikes appear in the ADC data and radiated emissions increase.
Evidence
The high-dV/dt copper creates strong capacitive coupling. SW-node area, not only trace resistance, controls the field.
Correction
Keep the SW node only as large as needed, contain it within the power stage, keep sensitive copper away on every layer and preserve a compact commutation loop.
CASE 04A fast signal crosses a split in its reference plane
The top-layer trace looks short and clean, but the ground plane beneath it has a slot.
A fast signal crosses a split in its reference plane
The top-layer trace looks short and clean, but the ground plane beneath it has a slot.
Likely symptom
Ringing, crosstalk, elevated common-mode radiation or failures that depend on cable attachment.
Evidence
The return current must detour around the split, increasing loop area and shared inductance.
Correction
Reroute over continuous reference copper. Do not “repair” the path with a distant stitching capacitor unless the interface and current path justify it.
CASE 05Connector pinout and net names are logically inconsistent
The schematic labels TX/RX from the MCU perspective, while the cable drawing labels them from the remote-device perspective.
Connector pinout and net names are logically inconsistent
The schematic labels TX/RX from the MCU perspective, while the cable drawing labels them from the remote-device perspective.
Likely symptom
The assembled board is electrically intact but the interface is dead or requires a crossed cable.
Evidence
DRC and connectivity checks pass because each net is internally consistent. The system-level interface definition is wrong.
Correction
Review the connector against the interface-control document, mating view and cable orientation. Use explicit names such as MCU_TX_TO_REMOTE_RX.
CASE 06BGA escape is routable in CAD but not manufacturable
Neck-down width, annular ring and via drill are below the selected fabricator's capability.
BGA escape is routable in CAD but not manufacturable
Neck-down width, annular ring and via drill are below the selected fabricator's capability.
Likely symptom
Fabricator rejection, yield loss, open vias or an unexpected move to expensive HDI processing.
Evidence
The footprint and rules were created from generic online values rather than the chosen stackup and drill process.
Correction
Agree the escape strategy with the fabricator before layout. Verify pad diameter, drill, annular ring, solder mask, via type and impedance neck-down limits.