Not videos. Not slides. Every module is a working interactive reference built from real engineering practice — concepts, diagrams, and applied problems you actually use.
Not videos. Not slides. Every module is a working interactive reference built from real engineering practice — concepts, diagrams, and applied problems you actually use.
AI writes the HDL — you make it work in silicon · LUTs, FFs, BRAM, DSP · The V-model · Course map
Write the spec before the HDL · Numbered, testable requirements · Timing budget · Interface contracts with waveforms
Block decomposition · Clock domain planning · BRAM/DSP pre-allocation · Architecture decisions with rationale
Type safety · Process semantics · Inference patterns · Self-checking testbench derived from the spec
Same design in Verilog · Blocking vs non-blocking · The shift-register collapse · AI-generated RTL error classes
RTL → netlist · Inference patterns · Reading the utilisation report as verification against M2 predictions
The four P&R phases · Fixed die topology · BUFG · Complete XDC traced to M1 · Bitstream for XC7A35T
Gate-level simulation · Logic equivalence checking · Catching synthesis-induced bugs before silicon
Setup/hold from bistable physics · WNS, TNS, WHS · Critical path line by line · Logic vs routing fixes
MTBF equation · Two-FF synchroniser · Grey code · ASYNC_REG · report_cdc · 1000-op integration scoreboard
ILA in-circuit capture at 100 MHz in silicon · Hardware waveforms match simulation · Full traceability matrix — every spec clause backed by physical evidence
Trace HDL down to LUT6, flip-flop, BRAM and DSP48, walk the V-model both directions, and answer questions that test physics rather than syntax. Learn by doing, not watching.
Module 3 builds the design in VHDL, Module 4 rebuilds the same design in Verilog. You see exactly where Verilog silently synthesises hardware VHDL would have caught.
Metastability, routing congestion, negative slack. The non-deterministic hardware failures that simulate clean and fail in the lab.